General: – IEEE 802.3 compatible Ethernet Controller – Integrated MAC and 10BASE-T PHY – 8 Kbyte Transmit/Receive Packet Dual Port Buffer SRAM – Programmable Automatic Retransmit on Collision – Programmable Padding and CRC Generation – Programmable Automatic Rejection of Erroneous Packets Buffer: – Configurable transmit/receive buffer size – Hardware managed circular receive FIFO – Byte-wide random and sequential access – Internal DMA for fast memory copying – Hardware assisted IP checksum calculation PHY: – Wave shaping output filter – Loopback mode MAC: – Support for Unicast, Multicast and Broadcast packets – Programmable pattern matching of up to 64 bytes within packet at user defined offset – Programmable wake-up on multiple packet formats, including Magic Packet®, Unicast, Multicast, Broadcast, specific packet match or any packet Packaging: – SOIC – SPDIP – SSOP – QFN (6×6 mm)
Voltage – Supply (Vcc/Vdd) | 3.1 V ~ 3.6 V |
Operating Temperature | -40°C ~ 85°C |
Package / Case | 28-SOIC (0.295″, 7.50mm Width) |