- C Compiler Optimized Architecture:
- Optional extended instruction set designed to optimize re-entrant code
- Up to 1024 bytes Data EEPROM
- Up to 64 Kbytes Linear program memory addressing
- Up to 3936 bytes Linear data memory addressing
- Up to 16 MIPS operation
- 16-bit wide instructions, 8-bit wide data path
- Priority levels for interrupts
- 31-level, software accessible hardware stack
- 8 x 8 single-cycle hardware multiplie
Core Size | 8-Bit |
Speed | 48MHz |
Peripherals | Brown-out Detect/Reset, HLVD, POR, PWM, WDT |
Number of I/O | 35 |
Program Memory Size | 64KB (32K x 16) |
Program Memory Type | FLASH |
EEPROM Size | 1K x 8 |
RAM Size | 3.8K x 8 |
Voltage – Supply | 1.8 V ~ 3.6 V |
Data Converters | A/D 14x10b |
Operating Temperature Range | -40°C ~ 125°C |
Package / Case | 44-TQFP |