DSPIC30F4013-30I/P

165,434 

IC DSC 16BIT 48KB FLASH 40DIP This section contains a brief overview of the CPU architecture of the dsPIC30F.The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant bit (LSb) always clear (refer to Section 3.1 “Program Address Space”), and the Most Significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.The working register array consists of 16-bit x 16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a Software Stack Pointer for interrupts and calls.The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory, AGU, which provides the appearance of a single, unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs,splitting the data address space into two parts (see Section 3.2 “Data Address Space”). The X and Y data space boundary is device-specific and cannot be altered by the user. Each data word consists of 2 bytes and most instructions can address data either as words or bytesDatasheet… Core Processor
dsPIC
Core Size
16-Bit
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Voltage – Supply (Vcc/Vdd)
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP